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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 10-bit 20 msps 160 mw cmos a/d converter ad876 features cmos 10-bit 20 msps sampling a/d converter pin-compatible 8-bit option power dissipation: 160 mw +5 v single supply operation differential nonlinearity: 0.5 lsb guaranteed no missing codes power down (standby) mode three-state outputs digital i/os compatible with +5 v or +3.3 v logic adjustable reference input small size: 28-lead soic, 28-lead ssop, or 48-lead thin quad flatpack (tqfp) product description the ad876 is a cmos, 160 mw, 10-bit, 20 msps analog-to- digital converter (adc). the ad876 has an on-chip input sample-and-hold amplifier. by implementing a multistage pipe- lined architecture with output error correction logic, the ad876 offers accurate performance and guarantees no missing codes over the full operating temperature range. force and sense con- nections to the reference inputs m inimize external voltage drops. the ad876 can be placed into a standby mode of operation reducing the power below 50 mw. the ad876s digital i/o interfaces to either +5 v or +3.3 v logic. digital output pins can be placed in a high impedance state; the format of the out- put is straight binary coding. the ad876s speed, resolution and single-supply operation ideally suit a variety of applications in video, multimedia, imag- ing, high speed data acquisition and communications. the ad876s low power and single-supply operation satisfy require- ments for high speed portable applications. its speed and reso- lution ideally suit charge coupled device (ccd) input systems such as color scanners, digital copiers, electronic still cameras and camcorders. the ad876 comes in a space saving 28-lead soic and 48-lead thin quad flatpack (tqfp) and is specified over the commercial (0 c to +70 c) temperature range. product highlights low power the ad876 at 160 mw consumes a fraction of the power of presently available 8- or 10-bit, video speed converters. power- down mode and single-supply operation further enhance its desirability in low power, battery operated applications such as electronic still cameras, camcorders and communication systems. very small package the ad876 comes in a 28-lead soic, 28-lead ssop, and 48- lead surface mount, thin quad flat package. the tqfp package is ideal for very tight, low headroom designs. digital i/o functionality the ad876 offers three-state output control. pin compatible upgrade path the ad876 offers the option of laying out designs for eight bits and migrating to 10-bit resolution if prototype results warrant. functional block diagram a/d d/a a/d d/a a/d d/a a/d correction logic ain reftf refts refbs refbf stby three- state (msb) d9 d0 (lsb) drv dd dv dd av dd clk drv ss dv ss av ss cml ad876 sha sha sha gain sha gain gain output buffers one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
ad876Cspecifications rev. b C2C ad876jr-8 ad876 parameter min typ max min typ max units resolution 8 10 bits dc accuracy integral nonlinearity (inl) 0.3 1.0 1.0 lsb differential nonlinearity (dnl) 0.1 0.75 0.5 1 lsb no missing codes guaranteed guaranteed offset error 0.1 0.4 % fsr gain error 0.1 0.2 % fsr analog input input range 2 2 v p-p input capacitance 5.0 5.0 pf reference input reference top voltage 3.5 4.0 4.5 3.5 4.0 4.5 v reference bottom voltage 1.6 2.0 2.5 1.6 2.0 2.5 v reference input resistance 250 250 w reference input current 8.0 8.0 ma reference top offset 35 35 mv reference bottom offset 35 35 mv dynamic performance effective number of bits f in = 1 mhz 7.8 9.0 bits f in = 3.58 mhz 7.4 7.8 8.2 9.0 bits f in = 10 mhz 7.5 8.2 bits signal-to-noise and distortion (s/n+d) ratio f in = 1 mhz 49 56 db f in = 3.58 mhz 46 49 51 56 db f in = 10 mhz 47 51 db total harmonic distortion (thd) f in =1 mhz C62 C62 db f in = 3.58 mhz C62 C56 C62 C56 db f in =10 mhz C60 C60 db spurious free dynamic range 2 C65 C65 db full power bandwidth 150 150 mhz differential phase 0.5 0.5 degree differential gain 1 1 % power supplies operating voltage av dd 1 +4.5 +5.25 +4.5 +5.25 volts dv dd 1 +4.5 +5.25 +4.5 +5.25 volts drv dd +3.0 +5.25 +3.0 +5.25 volts operating current iav dd 20 25 20 25 ma idv dd 12 16 12 16 ma idrv dd 0.1 1 0.1 1 ma power consumption 160 190 160 190 mw temperature range specified 0 +70 0 +70 c notes 1 av dd and dv dd must be within 0.5 v of each other to maintain specified performance levels. 2 3.58 mhz input frequency. specifications subject to change without notice. see definition of specifications for additional information. (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, drv dd = +3.3 v, v refb = +4.0 v, v refb = +2.0 v, f clock = 20 msps, unless otherwise noted)
ad876 rev. b C3C digital specifications ad876 parameter symbol drv dd min typ max units logic input high level input voltage v ih 3.0 2.4 v 5.0 4.0 v 5.25 4.2 v low level input voltage v il 3.0 0.6 v 5.0 1.0 v 5.25 1.05 v high level input current i ih 5.0 C10 +10 m a low level input current i il 5.0 C50 +50 m a low level input current (clk only) i il 5.0 C10 +10 m a input capacitance c in 5pf logic outputs high level output voltage v oh (i oh = 50 m a) 3.0 2.4 v 5.0 3.8 v (i oh = 0.5 ma) 5.0 2.4 v low level output voltage v ol (i ol = 50 m a) 3.6 0.7 v 5.25 1.05 v (i ol = 0.6 ma) 5.25 0.4 v output capacitance c out 5pf output leakage current i oz C10 10 m a specifications subject to change without notice. timing specifications symbol min typ max units maximum conversion rate 1 20 mhz clock period t c 50 ns clock high t ch 23 25 ns clock low t cl 23 25 ns output delay t od 10 20 ns pipeline delay (latency) 3.5 clock cycles aperture delay time 4 ns aperture jitter 22 ps note 1 conversion rate is operational down to 10 khz without degradation in specified performance. out data n-4 data n-3 data n-2 data n-1 data n sample n sample n+1 sample n+2 ain clk t cl t ch t c t od figure 1. timing diagram (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, drv dd = +3.3 v, v reft = +4.0 v, v refb = +2.0 v, f clock = 20 msps, c l = 20 pf unless otherwise noted)
rev. b C4C ad876 soic tqfp symbol pin no. pin no. type name and function d0 (lsb) 3 1 do least significant bit. d1Cd4 4C7 2C5 do data bits 1 through 4. d5Cd8 8C11 8C11 data bits 5 through 8. d9 (msb) 12 12 do most significant bit. three- 16 23 di three-state = low three-state = high state or n/c normal operating mode high impedance outputs stby 17 24 di stby = low or n/c stby = high normal operating mode standby mode clk 15 22 di clock input. cml 26 38 ao bypass pin for an internal bias point. reftf 22 30 ai reference top force. refbf 24 34 ai reference bottom force. refts 21 29 ai reference top sense. refbs 25 35 ai reference bottom sense. ain 27 39 ai analog input. av dd 28 42 p +5 v analog supply. av ss 1 44 p analog ground. dv dd 18 26 p +5 v digital supply. dv ss 14, 19, 20 17, 27, 28 p digital ground. drv dd 2 45 p +3.3 v/+5 v digital supply. supply for digital input and output buffers. drv ss 13 16 p +3.3 v/+5 v digital ground. ground for digital input and output buffers. type: ai = analog input; ao = analog output; di = digital input; do = digital output; p = power. pin configurations soic/ssop tqfp pin function descriptions pins d0 and d1 are left open for the ad876jr-8 * av ss drv dd av dd ain d2 d3 d4 refbf reftf * d0 * d1 cml refbs d5 refts d6 dv ss d7 dv ss d8 dv dd d9 stby drv ss three-state dv ss clk 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 8 21 9 20 10 19 11 12 17 16 14 15 top view (not to scale) ad876 nc nc = no connect refbs reftf refbf d0 d1 d4 d5 d6 d2 d3 dv ss dv dd refts d8 d9 d7 41 42 43 47 45 46 17 20 19 18 14 16 15 36 35 32 31 30 34 33 44 1 2 5 6 7 3 4 37 38 39 21 24 23 22 40 28 27 26 29 9 10 11 8 48 13 25 12 top view (not to scale) ad876 drv ss dv ss clk three-state stby drv dd av ss av dd ain cml dv ss
ad876 rev. b C5C ordering guide temperature package package model range description options ad876jr 0 c to +70 c 28-lead soic r-28 ad876jst-reel 0 c to +70 c 48-lead tqfp st-48 (tape and reel 13") ad876jr-8 0 c to +70 c 28-lead soic r-28 ad876ar C40 c to +85 c 28-lead soic r-28 ad876ars C40 c to +85 c 28-lead ssop rs-28 ad876jrs 0 c to +70 c 28-lead ssop rs-28 ad876jrs-8 0 c to +70 c 28-lead ssop rs-28 absolute maximum ratings* parameter with respect to min max units av dd av ss C0.5 +6.5 volts dv dd , drv dd dv ss , drv ss C0.5 +6.5 volts av ss dv ss , drv ss C0.5 +0.5 volts ain av ss C0.5 +6.5 volts refts, reftf refbs, refbf av ss C0.5 +6.5 volts digital inputs, clk dv ss , drv ss C0.5 +6.5 volts junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad876 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. figure 2. equivalent circuits reftf refts refbs refbf av dd av ss av dd av ss av dd av ss av dd av ss internal reference voltage internal reference voltage drv dd dv ss drv ss dv ss dv dd drv dd drv ss dv ss dv dd av dd av ss drv dd drv ss dv ss dv dd c) clk d) ain a) d0Cd9 b) three-state, standby warning! esd sensitive device
rev. b C6C ad876
ad876 rev. b C7C definitions of specifications integral nonlinearity (inl) integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb before the first code transi- tion. full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. it is often specified in terms of the resolution for which no missing codes (nmc) are guaranteed. offset error the first transition should occur at a level 1/2 lsb above zero. offset is defined as the deviation of the actual first code transition from that point. gain error the first code transition should occur for an analog value 1/2 lsb above nominal negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. new output data is provided every clock cycle. reference top/bottom offset resistance between the reference input and comparator input tap points causes offset errors. these errors can be nulled out by using the force-sense connection as shown in the reference input section. theory of operation the ad876 implements a pipelined multistage architecture to achieve high sample rate with low power. the ad876 distrib- utes the conversion over several smaller a/d subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. as a consequence of the distrib- uted conversion, the ad876 requ ires a small fraction of the 1023 comparators used in a traditional flash type a/d. a sample-and- hold function within each of the stages permits the first stage to operate on a new input sample while the second and third stages operate on the two preceding samples. applying the ad876 driving the analog input figure 11 shows the equivalent analog input of the ad876, a sample-and-hold amplifier (sha). bringing clk to a logic low level closes switches 1 and 2 and opens switch 3. the input source connected to ain must charge capacitor c h during this time. when clk transitions from logic low to logic high, switch 1 opens first, placing the sha in hold mode. switch 2 opens subsequently. switch 3 then closes, connects the feed- back loop around the op amp, and forces the output of the op amp to equal the voltage stored on c h . when clk transitions from logic high to logic low, switch 3 opens first. switch 2 closes and reconnects the input to c h . finally, switch 1 closes and places the sha in track mode. the structure of the input sha places certain requirements on the input drive source. the combination of the pin capacitance, c p , and the hold capacitance, c h , is typically less than 5 pf. the input source must be able to charge or discharge this ca- pacitance to 10-bit accuracy in one half of a clock cycle. when the sha goes into track mode, the input source must charge or discharge capacitor c h from the voltage already stored on c h (the previously captured sample) to the new voltage. in the worst case, a full-scale voltage step on the input, the input source must provide the charging c urrent through the r on (50 w ) of switch 2 and quickly settle (within 1/2 clk period). this situation corresponds to driving a low input impedance. on the other hand, when the source voltage equals the value previously stored on c h , the hold capacitor requires no input current and the equivalent input impedance is extremely high. adding series resistance between the output of the source and the ain pin reduces the drive requirements placed on the source. figure 12 shows this configuration. the bandwidth of the particular application limits the size of this resistor. to maintain the performance outlined in the data sheet specifica- tions, the resistor should be limited to 200 w or less. for appli- cations with signal bandwidths less than 10 mhz, the user may increase the size of the series resistor proportionally. alterna- tively, adding a shunt capacitance between the ain pin and 1 harmonics (dbc) 2nd C68.02 3rd C72.85 4th C70.68 5th C78.09 6th C77.74 7th C75.62 8th C75.98 9th C81.20 3 6 2 4 7 thd = C64.12 snr = 48.73 sinad = 48.61 sfdr = C68.02 9 8 5 figure 9. ad876jr-8 typical fft (f in = 3.58 mhz, ain = C0.5 db, f clock = 20 msps) 4 7 5 harmonics (dbc) 2nd C68.91 3rd C73.92 4th C68.67 5th C73.26 6th C80.55 7th C82.02 8th C81.02 9th C88.94 thd = C64.24 snr = 55.71 sinad = 55.14 sfdr = C68.67 9 6 3 1 8 2 figure 10. ad876 typical fft (f in = 3.58 mhz, ain = C0.5 db, f clock = 20 msps)
rev. b C8C ad876 20 khz. at a sample clock frequency of 20 mhz, the dc bias current at 3 v dc is approximately 30 m a. if we choose r2 equal to 1 k w and r1 equal to 50 w , the parallel capacitance should be a minimum of 0.008 m f to avoid attenuating signals close to 20 khz. note that the bias current will cause a 31.5 mv offset from the 3 v bias. in systems that must use dc-coupling, use an op amp to level- shift a ground-referenced signal to comply with the input requirements of the ad876. figure 14 shows an ad817 configured in inverting mode with ac signal gain of C1. the dc voltage at the noninverting input of the op amp controls the amount of dc level shifting. a resistive voltage divider attenu- ates the refbf signal. the op amp then multiplies the attenu- ated signal by 2. in the case where refbf = 1.6 v, the dc output level will be 2.6 v. the ad817 is a low cost, fast settling, single supply op amp with a g = C1 bandwidth of 29 mhz. the ad818 is similar to the ad817 but has a 50 mhz bandwidth. other appropriate op amps include the ad8011, ad812 (a dual), and the ad8001. ad817 or ad818 nc nc 0.1 m f +v cc r f = 4.99k v ain ad876 r in = 4.99k v 3k v 14.7k v refbf 2v p-p 0vdc figure 14. bipolar level shift an integrated difference amplifier such as the ad830 is an alternate means of providing dc level shifting. the ad830 provides a great deal of flexibility with control over offset and gain. figure 15 shows the ad830 precisely level-shifting a unipolar, ground-referenced signal. the reference voltage, refbs, determines the amount of level-shifting. the ac gain is 1. the ad830 offers the advantages of high cmrr, precise gain, offset, and high-impedance inputs when compared with a discrete implementation. for more information regarding the ad830, see the ad830 data sheet. ad876 ain C12v v b +2v 0 2v v b v b refbs 0.1 0.1 +12v ad830 figure 15. level shifting with the ad830 reference input driving the reference terminals the ad876 requires an external reference on pins reftf and refbf. the ad876 provides reference sense pins, refts and refbs, to minimize voltage drops caused by external and internal wiring resistance. a resistor ladder, nominally 250 w , connects pins reftf and refbf. analog ground can lower the ac source impedance. the value of this capacitance will depend on the source resistance and the required signal bandwidth. the input span of the ad876 is a function of the reference voltages. for more information regarding the input range, see the driving the reference terminals section of the data sheet. ad876 c p 2 3 c h ain 1 figure 11. ad876 equivalent input structure ain v s < < 200 v figure 12. simple ad876 drive requirements in many cases, particularly in single-supply operation, ac- coupling offers a convenient way of biasing the analog input signal at the proper signal range. figure 13 shows a typical configuration for ac-coupling the analog input signal to the ad876. maintaining the specifications outlined in the data sheet requires careful selection of the component values. the most important concern is the f - 3 db high-pass corner that is a function of r2, and the parallel combination of c1 and c2. the f - 3 db point can be approximated by the equation f - 3 db = 1 [2 p ( r 2) ceq ] where ceq is the parallel combination of c1 and c2. note that c1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. adding a small ceramic or polystyrene capacitor on the order of 0.01 m f that does not become inductive until negligibly higher frequencies maintains a low impedance over a wide frequency range. ain r1 ad876 v in c1 c2 r2 i b v bias 3v figure 13. ac-coupled inputs there are additional considerations when choosing the resistor values. the ac-coupling capacitors integrate the switching transients present at the input of the ad876 and cause a net dc bias current, i b , to flow into the input. the magnitude of this bias current increases with increasing dc signal level and also increases with sample frequency. this bias current will result in an offset error of (r1 + r2) i b . if it is necessary to compen- sate this error, consider making r2 negligibly small or modify- ing v bias to account for the resultant offset. as an example, assume that the input to the ad876 must have a dc bias of 3 v and the minimum expected signal frequency is
ad876 rev. b C9C figure 16 shows the equivalent input structure for the ad876 reference pins. there is approximately 5 w of resistance between both the reftf and refbt pins and the reference ladder. if the force-sense connections are not used, the voltage drop across the 5 w resistors will result in a reduced voltage appear- ing across the ladder resistance. this reduces the input span of the converter. apply ing a slightly larger span between the reftf and refbf pins compensates this error. note that the tem- perature coefficients of the 5 w resistors are 1350 ppm. the user should consider the effects of temperature when not using a force-sense reference configuration. ad876 reftf refts refbs refbf 5 v dacs c (v in ) clk clk 5 v v1 v2 250 v r ladder figure 16. ad876 equivalent reference structure do not connect the refts and refbs pins in configurations that do not use a force-sense reference. connecting the force and sense lines together allows current to flow in the sense lines. any current allowed to flow through these lines must be negligi- bly small. current flow causes voltage drops across the resis- tance in the sense lines. because the internal d/as of the ad876 tap different points along the sense lines, each d/a would receive a slightly different reference voltage if current were flowing in these wires. to avoid this undesirable condition, leave the sense lines unconnected. any current allowed to flow through these lines must be negligibly small (<100 m a). the voltage drop across the internal resistor ladder determines the input span of the ad876. the driving voltages required at the v1 and v2 points are respectively +4 v and +2 v. calculate the full-scale input span from the equation input span ( v ) = refts refbs this results in a full-scale input span of approximately +2 v when refts = +4 v and refbs = +2 v in order to maintain the requisite 2 v drop across the internal ladder, the external reference must be capable of providing approximately 8.0 ma. the user has flexibility in determining both the full-scale span of the analog input and where to center this voltage. figure 17 shows the range over which the ad876 can operate without degrading the typical performance. 2.5 3.0 3.5 4.0 4.5 1.0 1.5 2.0 2.5 3.0 refbf, refbs reftf, refts (1.6, 4.5) (2.5, 4.5) (1.6, 3.5) (2.5, 3.5) figure 17. ad876 reference ranges while the previous issues address the dc aspects of the ad876 reference, the user must also be aware of the dynamic imped- ance changes associated with the reference inputs. the simpli- fied diagram of figure 16 shows that the reference pins connect to a capacitor for one-half of the clock period. the size of the capacitor is a function of the analog input voltage. the external reference must be able to maintain a low imped- ance over all frequencies of interest in order to provide the charge required by the capacitance. by supplying the requisite charge, the reference voltages will be relatively constant and perfor- mance will not degrade. for some reference configurations, voltage transients will be present on the reference lines; this is particularly true during the falling edge of clk. it is impor- tant that the reference recovers from the transients and settles to the desired level of accuracy prior to the rising edges of clk. there are several reference configurations suitable for the ad876 depending on the application, desired level of accuracy, and cost trade-offs. the simplest configuration, shown in fig- ure 18, utilizes a resistor string to generate the reference volt- ages from the converters analog power supply. the 0.1 m f bypass capacitors effectively reduce high-frequency transients. the 10 m f capacitors act to reduce the impedances at the reftf and refbf pins at lower frequencies. as input fre- quencies approach dc, the capacitors become ineffective, and small voltage deviations will appear across the biasing resistors. this application can maintain 10-bit accuracy for input frequen- cies above approximately 200 hz. 8-bit applications can use this circuit for input frequencies above approximately 50 hz. +5v ad876 10 m f 10 m f 0.1 m f 10 m f 0.1 m f 250 v ( 6 1%) 2v nc nc 4v 140 v ( 6 1%) 250 v ( 6 15%) refts reftf refbf refbs nc = no connect figure 18. low cost reference circuit this reference configuration provides the lowest cost but has several disadvantages. these disadvantages include poor dc power supply rejection and poor accuracy due to the variability of the internal and external resistors. the ad876 offers force-sense reference connections to elimi- nate the voltage drops associated with the internal connections to the reference ladder. figure 19 shows a suggested circuit using an ad826 dual, high speed op amp. this configuration uses 3.6 v and 1.6 v reference voltages for reft and refb, respectively. the connections shown in figure 19 configure the op amps as voltage followers.
rev. b C10C ad876 ad876 +5v 8 6 5 7 1/2 ad826 2 3 6 1/2 ad826 4 reft refb refts reftf refbs refbf c3 0.1 m f c4 0.1 m f c2 0.1 m f c5 0.1 m f c1 0.1 m f figure 19. kelvin connected reference using the ad826 by connecting the op amp feedback through the sense connec- tions of the ad876, the outputs of the op amps automatically adjust to compensate for the voltage drops that occur within the converter. the ad826 has the advantage of being able to maintain stability while driving unlimited capacitive loads. as a result, 0.1 m f capacitors c1, c2, and c3 can connect directly to the outputs of the op amps. these decoupling capacitors reduce high frequency transients. capacitors c4 and c5 shunt across the internal resistors of the force sense connections and prevent instability. this configuration provides excellent performance and a mini- mal number of components. the circuit also offers the advan- tage of operating from a single +5 v supply. while alternative op amps may also be suitable, consider the stability of these op amps while driving capacitive loads. the circuit shown in figure 20 allows a wider selection of op amps when compared with the previous configuration. an ad876 1/2 op-295 10 m f 0.1 m f reft refts reftf 47nf 20k v 10 v 1/2 op-295 10 m f 0.1 m f refb refbs refbf 47nf 20k v 10 v 22 m f figure 20. kelvin connected reference using the op295 op295 dual, single-supply op amp provides stable 3.6 v and 1.6 v reference voltages. the ad822 dual op amp is also suit- able for single-supply applications. each half of the op295 is compensated to drive the 10 m f and 0.1 m f decoupling capaci- tors at the reftf and refbf pins and maintain stability. like any high resolution converter, the layout and decoupling of the reference is critical. the actual voltage digitized by the ad876 is relative to the reference voltages. in figure 21, for example, the reference return and the bypass capacitors are connected to the shield of the incoming analog signal. distur- bances in the ground of the analog input, that will be common- mode to the reft, refb, and ain pins because of the common ground, are effectively removed by the ad876s high common-mode rejection. high frequency noise sources, v n1 and v n2 , are shunted to ground by decoupling capacitors. any voltage drops between the analog input ground and the reference bypassing points will be treated as input signals by the converter via the reference inputs. consequently, the reference decoupling capacitors should be connected to the same analog ground point used to define the analog input voltage. (for further suggestions, see the grounding and layout rules section of the data sheet.) 4v v n1 2v v n2 reftf refbf ain ad876 figure 21. recommended bypassing for the reference inputs clock input the ad876 clock input is buffered internally with an inverter powered from the drv dd pin. this feature allows the ad876 to accommodate either +5 v or +3.3 v cmos logic input sig- nal swings with the input threshold for the clk pin nominally at drv dd /2. the ad876s pipelined architecture operates on both rising and falling edges of the input clock. to minimize duty cycle varia- tions the recommended logic family to drive the clock input is high speed or advanced cmos (hc/hct, ac/act) logic. cmos logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 msps operation. the ad876 is designed to support a conversion rate of 20 msps; running the part at slightly faster clock rates may be possible, although at reduced performance levels. conversely, some slight performance improvements might be realized by clocking the ad876 at slower clock rates. the power dissipated by the correction logic and output buffers is largely proportional to the cl ock frequency; running at reduced clock rates provides a reduction in power consumption. figure 8 illustrates this trade-off. digital inputs and outputs each of the ad876 digital control inputs, three-state and stby, has an input buffer powered from the drv dd supply pins. with drv dd set to +5 v, all digital inputs readily inter- face with +5 v cmos logic. for interfacing with lower voltage cmos logic, drv dd can be set to 3.3 v, effectively lowering the nominal input threshold of all digital inputs to 3.3 v/2 = 1.65 v. the format of the digital output is straight binary. table i shows the output format for the case where refts = 4 v and refbs = 2 v.
ad876 rev. b C11C for drv dd = 5 v, the ad876 output signal swing is compat- ible with both high speed cmos and ttl logic families. for ttl, the ad876 on-chip, output drivers were d esigned to support several of the high speed ttl families (f, as, s). for applications where the clock rate is below 20 msps, other ttl families may be appropriate. for interfacing with lower voltage cmos logic, the ad876 sustains 20 msps operation with drv dd = 3.3 v. in all cases, check your logic family data sheets for compatibility with the ad876 digital specification table. three-state outputs the digital outputs of the ad876 can be placed in a high im- pedance state by setting the three-state pin to high. this feature is provided to facilitate in-circuit testing or evaluation. note that this function is not intended for enabling/ disabling the adc outputs from a bus at 20 msps. also, to avoid corruption of the sampled analog signal during conversion (3.5 clock cycles), it is highly recommended that the ad876 outputs be enabled on the bus prior to the first sampling. for the purpose of budgetary timing, the maximum access and float delay times (t dd , t hl shown in figure 15) for the ad876 are 150 ns. three-state active high impedance d0Cd9 t dd t hl figure 22. high-impedance output timing diagram table i. output data format approx. three- data ain (v) state d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 >4 0 1111111111 4 0 1111111111 3 0 1000000000 2 0 0000000000 <2 0 0000000000 x 1 zzzzzzzzzz a low power mode feature is provided such that for stby = high and the clock disabled, the static power of the ad876 will drop below 50 mw. grounding and layout rules as is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. the analog and digital grounds on the ad876 have been separated to optimize the management of return currents in a system. it is recommended that a printed circuit board (pcb) of at least 4 layers employing a ground plane and power planes be used with the ad876. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation, and ground plane. these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvement in performance. it is important to design a layout which prevents noise from coupling onto the input signal. digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. separate analog and digital grounds should be joined together directly under the ad876. a solid ground plane under the ad876 is also acceptable if the power and ground return currents are managed carefully. a general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. for further layout suggestions, see the ad876 evaluation board data sheet . digital outputs each of the on-chip buffers for the ad876 output bits (d0Cd9) is powered from the drv dd supply pins, separate from av dd or dv dd . the output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy gener- ated. in all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pf level.
rev. b C12C ad876 figure 23. ad876 evaluation board schematic p1 2 p1 4 p1 6 p1 8 p1 10 p1 12 p1 14 p1 16 p1 18 p1 20 p1 22 p1 24 p1 28 p1 30 p1 32 p1 34 p1 36 p1 38 p1 40 p1 26 clk 3_state stby dv dd subst nc refts reftf nc refbf refbs cml ain av dd dv ss drv ss db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 drv dd av ss + + + +5vd jp1 c62 0.1 m f stby vp6 c50 10 m f refts vp3 refbf vp2 vp4 refbs c4 10 m f r17 1.13k v r16 1k v r14 100 v dc_in reftf vp1 ain j2 tp2 r15 51 v c1 0.1 m f jp5 tp18 ext_cm 23 1 int_cm r18 1k v +5vd jp4 vp8 refts reftf refbf refbs c64 0.1 m f c56 0.1 m f c2 10 m f +5va g1 g2 a7 a6 a5 a4 a3 a2 a1 a0 y7 y6 y5 y4 y3 y2 y1 y0 u3 g1 g2 a7 a6 a5 a4 a3 a2 a1 a0 y7 y6 y5 y4 y3 y2 y1 y0 u2 74als541 + + u1 ad876 14 13 12 11 10 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 5 6 7 8 9 9 8 7 6 5 4 3 2 19 1 11 12 13 14 15 16 17 18 d5 d6 d7 d8 d9 0 1 2 4 9 8 7 6 4 3 2 19 1 5 11 12 13 14 15 16 17 18 d0 d1 d2 d3 d4 3 74als541 u4 74f04 u4 74f04 1 2 jp2 tp4 clk_in tp1 j1 r1 51 v 3st vp5 c3 47 m f +5vd c49 10 m f c54 0.1 m f d9 d8 d5 d7 d6 d4 d3 d0 d2 d1 r2 * r3 * r4 * r5* r6* r7* r8 * r9* r10* r11 * r12 * p1 1 p1 3 p1 5 p1 7 p1 9 p1 11 p1 13 p1 15 p1 17 p1 19 p1 21 p1 23 p1 27 p1 29 p1 31 p1 33 p1 35 p1 37 p1 39 p1 25 4 3 tp3 * r2Cr12 = 20 v
ad876 rev. b C13C figure 25. silkscreen layer, circuit side pcb layout figure 24. s ilkscreen layer, component side pcxb layout
rev. b C14C ad876 figure 27. circuit side pcb layout figure 26. component side pcb layout
ad876 rev. b C15C figure 29. power layer pcb layout figure 28. ground layer pcb layout
rev. b C16C ad876 outline dimensions dimensions shown in inches and (mm). r-28 28-lead wide body (soic) 28 15 14 1 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 st-48 28-lead plastic thin quad flatpack (tqfp) top view (pins down) 1 36 37 48 12 13 25 24 0.276 0.004 (7.0 0.1) sq 0.354 0.008 (9.00 0.2) sq 0.039 (1.00) ref 0.02 0.003 (0.50 0.08) 0.007 +0.003 ?.001 (0.18 +0.08 ?.03) seating plane 0.055 0.002 (1.40 0.05) 0.059 +0.008 ?.004 (1.50 +0.2 ?.1) 0.02 0.008 (0.5 0.2) 0.005 +0.002 ?.0008 (0.127 +0.05 ?.02) 0.004 0.002 (0.1 0.05) 0 min (3.5 3.5 ) rs-28 28-lead shrink small outline package (ssop) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 printed in u.s.a. c1991aC0C1/98

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